1. Field of the Invention
The present invention relates to a semiconductor device provided with bipolar transistors formed on a semiconductor substrate, and its manufacturing method, and more particularly to a semiconductor device having bipolar transistors formed in respective wells provided in a semiconductor substrate, and its manufacturing method.
2. Description of the Related Art
Methods of various kinds which do not employ epitaxially grown layers as a method of manufacturing a semiconductor device having bipolar transistors on a silicon substrate have been proposed in the past.
For example, a method of forming well regions of MOSFETs and well regions of bipolar transistors by a simultaneous ion implantation in the manufacture of a semiconductor device in which the MOSFETs and the bipolar transistors are formed on an identical substrate, has been disclosed in Publication of Unexamined Patent Applications, No. Hei 4-180260.
Here, referring to FIG. 23, the method of manufacturing a semiconductor device mentioned in the Publication will be described briefly. As shown in FIG. 23, the semiconductor device has an NPN bipolar transistor, a PNP bipolar transistor, an nMOS transistor, and a PMOS transistor on an identical p-type silicon substrate.
In the manufacturing method in the above, an n-type collector of the NPN bipolar transistor and an n-type well region 23 of the pMOS transistor, and a p-type collector of the PNP bipolar transistor and a p-type well region 26 of the nMOS transistor are formed by the same ion implantations, respectively. In this method, only the two steps of forming the well region 23 and the well region 26 suffice for the purpose by sharing the wells without using epitaxially grown layers. Accordingly, the element characteristics are superior and the step number does not increase compared with the conventional method.
Now, the formation of a mask is a time and cost consuming work that requires many processings such as coating of a photoresist film, exposure, fixation, mask inspection, and the like. Moreover, an increasingly longer time is being required for positioning of the mask because of the decreasing margin in the positional deviation accompanying the refinements in the integrated circuits.
Accordingly, the formation of prescribed impurity regions by ion implantations using a smaller number of masks is extremely important for the manufacture of a semiconductor device with high fabrication precision through reduction in the manufacturing cost. At the same time, it is becoming important to make the characteristics of individual elements in the semiconductor device to be optimized and highly efficient accompanying the development in the high performance and composite functioning of the semiconductor device.
Although the above invention proposes a cost effective method of formation of the well regions of the MOS transistors and the collector regions of the bipolar transistors, it is not possible to optimize the characteristics of the respective elements.
According to the method in the Publication, the n-type collector of the NPN transistor and the n-type well of the pMOS transistor, and the p-type collector of the PNP transistor and the p-type well of the nMOS are formed respectively by the same ion implantations, as shown in FIG. 23. By so doing, it is claimed that a reduction in the number of manufacturing steps can be realized.
Now, when the gate length of the MOS transistors is decreased, the threshold voltages of the n-type well of the pMOS transistor and the p-type well of the nMOS transistor are reduced due to the short channel effect. As a countermeasure against this, it is general to suppress the short channel effect by raising the impurity concentration of the wells of the MOS transistors.
However, according to the method in the Publication, the n-type collector of the NPN transistor and the n-type well (the n well 23 in FIG. 23) of the pMOS transistor, and the p-type collector of the PNP transistor and the p-type well (the p well 26 in FIG. 23) of the nMOS transistor are respectively shared by each other. Therefore, when the impurity concentrations of the wells of the MOS transistors are raised, the impurity concentrations of the collectors of the bipolar transistors are also raised, and their base-collector junction breakdown strengths are lowered. That is, if the transistor characteristics of the MOS transistors are enhanced, the transistor characteristics of the bipolar transistors are degraded, and on the contrary, if the transistor characteristics of the bipolar transistors are enhanced, the transistor characteristics of the MOS transistors are degraded. Consequently, it is difficult to simultaneously obtain satisfactory transistor characteristics for both of the MOS transistors and the bipolar transistors.